DLX_verilog\dlx.v
...........\dlx.v.bak
...........\DLX_verilog.cr.mti
...........\DLX_verilog.mpf
...........\machine.v
...........\memory.v
...........\memory.v.bak
...........\regfile.v
...........\tb.do
...........\tb.do.bak
...........\testbench.v
...........\vsim.wlf
...........\work\dlx\verilog.prw
...........\....\...\verilog.psm
...........\....\...\_primary.dat
...........\....\...\_primary.dbs
...........\....\...\_primary.vhd
...........\....\memory\verilog.prw
...........\....\......\verilog.psm
...........\....\......\_primary.dat
...........\....\......\_primary.dbs
...........\....\......\_primary.vhd
...........\....\regfile\verilog.prw
...........\....\.......\verilog.psm
...........\....\.......\_primary.dat
...........\....\.......\_primary.dbs
...........\....\.......\_primary.vhd
...........\....\test\verilog.prw
...........\....\....\verilog.psm
...........\....\....\_primary.dat
...........\....\....\_primary.dbs
...........\....\....\_primary.vhd
...........\....\_info
...........\....\.temp\vlog26h6db
...........\....\.....\vlog9v5nbh
...........\....\.....\vlogeihfy4
...........\....\.....\vlogi5ms72
...........\....\.....\vlogjxrae8
...........\....\.....\vlogyaxrtf
...........\....\_vmake
...........\....\dlx
...........\....\memory
...........\....\regfile
...........\....\test
...........\....\_temp
...........\work
DLX_verilog