Description: Verilong HDL is one of the most frequenctly used hardware description language because of its simple and convenient properties. This course aimes to design a digital clock equipped with the fundamatal functions of 4-segment display, stopwatch and time setting even some additional ones using this language . The implement of the designed clock is contributed by DE1 board
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as1\as1.asm.rpt
...\as1.bdf
...\as1.bsf
...\as1.cdf
...\as1.done
...\as1.dpf
...\as1.fit.rpt
...\as1.fit.smsg
...\as1.fit.summary
...\as1.flow.rpt
...\as1.map.rpt
...\as1.map.smsg
...\as1.map.summary
...\as1.pin
...\as1.pof
...\as1.qpf
...\as1.qsf
...\as1.qws
...\as1.sof
...\as1.tan.rpt
...\as1.tan.summary
...\as1.v
...\as1.v.bak
...\as1_assignment_defaults.qdf
...\as2.bsf
...\as2.v
...\as2.v.bak
...\as3.bsf
...\as3.inc
...\as3.v
...\as3.v.bak
...\as4.bsf
...\as4.v
...\as4.v.bak
...\Block1.bdf
...\db\as1.db_info
...\..\as1.eco.cdb
...\..\as1.map.qmsg
...\..\as1.sld_design_entry.sci
...\..\prev_cmp_as1.asm.qmsg
...\..\prev_cmp_as1.fit.qmsg
...\..\prev_cmp_as1.map.qmsg
...\..\prev_cmp_as1.tan.qmsg
...\..\wed.wsf
...\digit.vwf
...\disp.bsf
...\f_clk.bsf
...\minute_second.bsf
...\prev_cmp_as1.qmsg
...\stop.vwf
...\db
as1
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