Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: 32bit_adder Download
 Description: Thirty-two adder designed to complement, addition and subtraction operations and overflow flag
 Downloaders recently: [More information of uploader 田小新]
 To Search:
File list (Check if you may need any files): 
 

adder_32_tb.v
adder_32.v

CodeBus www.codebus.net