Description: CMOS cameras turn VGA output based on the FPGA program source code, based on the DE2 board.
To Search:
File list (Check if you may need any files):
arm_VGA4
........\CMOS_Capture.v
........\CMOS_Capture.v.bak
........\db
........\DE2_D5M.asm.rpt
........\DE2_D5M.cdf
........\DE2_D5M.done
........\DE2_D5M.fit.rpt
........\DE2_D5M.fit.smsg
........\DE2_D5M.fit.summary
........\DE2_D5M.flow.rpt
........\DE2_D5M.jdi
........\DE2_D5M.map.rpt
........\DE2_D5M.map.summary
........\DE2_D5M.pin
........\DE2_D5M.pof
........\DE2_D5M.qpf
........\DE2_D5M.qsf
........\DE2_D5M.qws
........\DE2_D5M.sof
........\DE2_D5M.sta.rpt
........\DE2_D5M.sta.summary
........\DE2_D5M.tan.rpt
........\DE2_D5M.tan.summary
........\DE2_D5M.tis_db_list.ddb
........\DE2_D5M.v
........\DE2_D5M.v.bak
........\DE2_D5M_assignment_defaults.qdf
........\greybox_tmp
........\...........\cbx_args.txt
........\I2C_AV_Config.v
........\I2C_AV_Config.v.bak
........\I2C_Controller.v
........\I2C_OV7670_Config.v
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\DE2_D5M.db_info
........\..............\...................\DE2_D5M.root_partition.cmp.cdb
........\..............\...................\DE2_D5M.root_partition.cmp.dfp
........\..............\...................\DE2_D5M.root_partition.cmp.hdb
........\..............\...................\DE2_D5M.root_partition.cmp.kpt
........\..............\...................\DE2_D5M.root_partition.cmp.logdb
........\..............\...................\DE2_D5M.root_partition.cmp.rcfdb
........\..............\...................\DE2_D5M.root_partition.map.cdb
........\..............\...................\DE2_D5M.root_partition.map.dpi
........\..............\...................\DE2_D5M.root_partition.map.hbdb.cdb
........\..............\...................\DE2_D5M.root_partition.map.hbdb.hb_info
........\..............\...................\DE2_D5M.root_partition.map.hbdb.hdb
........\..............\...................\DE2_D5M.root_partition.map.hbdb.sig
........\..............\...................\DE2_D5M.root_partition.map.hdb
........\..............\...................\DE2_D5M.root_partition.map.kpt
........\..............\README
........\MY_FPGA_BOARD.tcl
........\output_file.jic
........\output_file.map
........\pass.txt
........\PLLJ_PLLSPE_INFO.txt
........\Sdram_Control_4Port
........\...................\command.v
........\...................\control_interface.v
........\...................\Sdram_Control_4Port.v
........\...................\Sdram_Control_4Port.v.bak
........\...................\Sdram_Params.h
........\...................\Sdram_PLL.ppf
........\...................\Sdram_PLL.qip
........\...................\Sdram_PLL.v
........\...................\Sdram_PLL_wave0.jpg
........\...................\Sdram_PLL_waveforms.html
........\...................\Sdram_RD_FIFO.qip
........\...................\Sdram_RD_FIFO.v
........\...................\Sdram_WR_FIFO.qip
........\...................\Sdram_WR_FIFO.v
........\...................\sdr_data_path.v
........\sdram_pll.qip
........\Sdram_RD_FIFO.qip
........\Sdram_WR_FIFO.qip
........\serv_req_info.txt
........\V
........\.\CCD_Capture.v
........\.\CCD_Capture.v.bak
........\.\I2C_CCD_Config.v
........\.\I2C_CCD_Config.v.bak
........\.\I2C_Controller.v
........\.\Line_Buffer.bsf
........\.\Line_Buffer.v
........\.\RAW2RGB.v
........\.\RAW2RGB.v.bak
........\.\Reset_Delay.v
........\.\Reset_Delay.v.bak
........\.\sdram_pll.bsf
........\.\sdram_pll.cmp
........\.\sdram_pll.inc
........\.\sdram_pll.ppf
........\.\sdram_pll.qip
........\.\sdram_pll.v
........\.\sdram_pll_bb.v
........\.\sdram_pll_inst.v
........\.\sdram_pll_syn.v
........\.\sdram_pll_wave0.jpg
........\.\sdram_pll_waveforms.html
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