Description: This a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU differences that each of the five pipeline stages maintenance a variable (SelType) indicates that the currently executing instruction types, this treatment data Adventure loaduse adventure or jump adventure when each segment can know The statement is being processed, in order to facilitate our processing.
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File list (Check if you may need any files):
PipelineCPU\ALU.v
...........\db\add_sub_gvd.tdf
...........\..\altsyncram_2rc1.tdf
...........\..\altsyncram_9g31.tdf
...........\..\altsyncram_a981.tdf
...........\..\altsyncram_eb01.tdf
...........\..\altsyncram_g981.tdf
...........\..\altsyncram_sng1.tdf
...........\..\cmpr_6cc.tdf
...........\..\cntr_ikf.tdf
...........\..\cntr_kkf.tdf
...........\..\logic_util_heursitic.dat
...........\..\mux_dqc.tdf
...........\..\mux_ioc.tdf
...........\..\mux_joc.tdf
...........\..\PipelineCPU.cbx.xml
...........\..\PipelineCPU.cmp.rdb
...........\..\PipelineCPU.cmp_merge.kpt
...........\..\PipelineCPU.db_info
...........\..\PipelineCPU.eco.cdb
...........\..\PipelineCPU.eds_overflow
...........\..\PipelineCPU.fnsim.cdb
...........\..\PipelineCPU.fnsim.hdb
...........\..\PipelineCPU.fnsim.qmsg
...........\..\PipelineCPU.hier_info
...........\..\PipelineCPU.hif
...........\..\PipelineCPU.lpc.html
...........\..\PipelineCPU.lpc.rdb
...........\..\PipelineCPU.lpc.txt
...........\..\PipelineCPU.map.bpm
...........\..\PipelineCPU.map.cdb
...........\..\PipelineCPU.map.ecobp
...........\..\PipelineCPU.map.hdb
...........\..\PipelineCPU.map.kpt
...........\..\PipelineCPU.map.logdb
...........\..\PipelineCPU.map.qmsg
...........\..\PipelineCPU.map_bb.cdb
...........\..\PipelineCPU.map_bb.hdb
...........\..\PipelineCPU.map_bb.logdb
...........\..\PipelineCPU.PipelineCPU0.rtl.mif
...........\..\PipelineCPU.pre_map.cdb
...........\..\PipelineCPU.pre_map.hdb
...........\..\PipelineCPU.rtlv.hdb
...........\..\PipelineCPU.rtlv_sg.cdb
...........\..\PipelineCPU.rtlv_sg_swap.cdb
...........\..\PipelineCPU.sgdiff.cdb
...........\..\PipelineCPU.sgdiff.hdb
...........\..\PipelineCPU.sim.cvwf
...........\..\PipelineCPU.sim.hdb
...........\..\PipelineCPU.sim.qmsg
...........\..\PipelineCPU.sim.rdb
...........\..\PipelineCPU.simfam
...........\..\PipelineCPU.sld_design_entry.sci
...........\..\PipelineCPU.sld_design_entry_dsc.sci
...........\..\PipelineCPU.syn_hier_info
...........\..\PipelineCPU.tis_db_list.ddb
...........\..\PipelineCPU.tmw_info
...........\..\prev_cmp_PipelineCPU.map.qmsg
...........\..\prev_cmp_PipelineCPU.qmsg
...........\..\prev_cmp_PipelineCPU.sim.qmsg
...........\..\shift_taps_m1m.tdf
...........\..\shift_taps_q1m.tdf
...........\..\shift_taps_t1m.tdf
...........\..\wed.wsf
...........\Imem.v
...........\Imem.v.bak
...........\incremental_db\compiled_partitions\PipelineCPU.root_partition.map.atm
...........\..............\...................\PipelineCPU.root_partition.map.cdb
...........\..............\...................\PipelineCPU.root_partition.map.dpi
...........\..............\...................\PipelineCPU.root_partition.map.hdb
...........\..............\...................\PipelineCPU.root_partition.map.hdbx
...........\..............\...................\PipelineCPU.root_partition.map.kpt
...........\..............\README
...........\left2.v
...........\left2.v.bak
...........\memory.v
...........\memory.v.bak
...........\PipelineCPU.qpf
...........\PipelineCPU.qsf
...........\PipelineCPU.qws
...........\PipelineCPU.rar
...........\PipelineCPU.v
...........\PipelineCPU.v.bak
...........\PipelineCPU.vwf
...........\PLUS.v
...........\PLUS.v.bak
...........\register.v
...........\register.v.bak
...........\..lease\PipelineCPU.done
...........\.......\PipelineCPU.flow.rpt
...........\.......\PipelineCPU.map.rpt
...........\.......\PipelineCPU.map.smsg
...........\.......\PipelineCPU.map.summary
...........\.......\PipelineCPU.sim.rpt
...........\Shift.v
...........\signedextend.v
...........\incremental_db\compiled_partitions
...........\db
...........\incremental_db
...........\release
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