Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: div_clk Download
 Description: A 20M to 16M clock frequency applet. There are some loopholes Please correct itself
 Downloaders recently: [More information of uploader yang]
 To Search:
File list (Check if you may need any files): 
 

div_clk.vt
div_clk.v

CodeBus www.codebus.net