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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: cordic_pipelined Download
 Description: This an implementation of CORDIC algorithm in verilog HDL, which contains design code and testbench.
 Downloaders recently: [More information of uploader zhouwen]
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cordic_cell.v
cordic_pipelined.v
cordic_tb.v

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