- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2013-06-05
- Downloads:
- 0 Times
- Uploaded by:
- 叶韬
Description: write vhdl natural logarithm, cordic iterate through the results. Improve the accuracy of the need to increase the number of iterations.
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ln.vhd
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