Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: Synchronous_Design-of-huawei Download
 Description: Huawei making FPGA/CPLD design and timing match against glitch synchronization strategies adopted
 Downloaders recently: [More information of uploader 张炽]
 To Search:
File list (Check if you may need any files): 
 

华为同步电路设计规范.pdf

CodeBus www.codebus.net