Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: series_rxd_timing Download
 Description: Receive asynchronous serial data, the data is written to the receiving fifo, you can set the timeout to receive multi-byte data, set the timeout period when the data does not appear, ready signal is valid, that receives complete packet, the data can be read from the fifo.
 Downloaders recently: [More information of uploader ppt555]
 To Search:
File list (Check if you may need any files):
 

series_rxd_timing\rxd_fifo_8_1024.xco
.................\rxd_fifo_8_16.xco
.................\rxd_fifo_8_256.xco
.................\rxd_fifo_8_64.xco
.................\series_rxd_timing.v
series_rxd_timing
    

CodeBus www.codebus.net