state_classic prepared using the VHDL language, we - CodeBus

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Title: state_classic

Category:
VHDL-FPGA-Verilog
Tags:
[Text]
File Size:
1.19kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
xurongwang

Description: prepared using the VHDL language, we can use MODELSIM simulation. For beginners, the more valuable reference.

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