Description: 4 RISC cpu design, digital circuit and logic of curriculum design, microprocessors and digital circuits for learning or helpful for students
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实验报告.doc
CPU\AM2901.vhd
...\automake.log
...\bitgen.ut
...\controllor.vhd
...\coregen.log
...\coregen.prj
...\cpu.bgn
...\cpu.bit
...\cpu.bld
...\cpu.cmd_log
...\cpu.drc
...\cpu.lso
...\cpu.mrp
...\cpu.nc1
...\cpu.ncd
...\cpu.ngc
...\cpu.ngd
...\cpu.ngm
...\cpu.ngr
...\cpu.pad
...\cpu.pad_txt
...\cpu.par
...\cpu.pcf
...\cpu.placed_ncd_tracker
...\cpu.prj
...\cpu.routed_ncd_tracker
...\cpu.stx
...\cpu.syr
...\cpu.twr
...\cpu.twx
...\cpu.ut
...\CPU.vhd
...\cpu.xpi
...\cpu_last_par.ncd
...\cpu_map.ncd
...\cpu_map.ngm
...\cpu_pad.csv
...\cpu_pad.txt
...\cpu_port.cel
...\cpu_port.lfp
...\cpu_port.ucf
...\cpu_port.ucf.bak
...\cpu_port.ucf.untf
...\data_IB.vhd
...\TH-UNION+.dhp
...\TH-UNION+.npl
...\TH-UNION+.zip
...\transcript
...\untitled.cdf
...\userlang.tpl
...\xst\work\hdllib.ref
...\...\....\hdpdeps.ref
...\...\....\sub00\vhpl00.vho
...\...\....\.....\vhpl01.vho
...\...\....\.....\vhpl02.vho
...\...\....\.....\vhpl03.vho
...\...\....\.....\vhpl04.vho
...\...\....\.....\vhpl05.vho
...\...\....\.....\vhpl06.vho
...\...\....\.....\vhpl07.vho
...\zhang.dhp
...\_impact.cmd
...\_impact.log
...\.ngo\netlist.lst
...\_pace.ucf
...\._projnav\bitgen.rsp
...\.........\coregen.rsp
...\.........\cpu.xst
...\.........\cpu_ncdTOut_tcl.rsp
...\.........\ednTOngd_tcl.rsp
...\.........\map.log
...\.........\nc1TOncd_tcl.rsp
...\.........\par.log
...\.........\parentAssignPackagePinsApp_tcl.rsp
...\.........\parentCreateTimingConstraintsApp_tcl.rsp
...\.........\parentEditConstraintsTextApp_tcl.rsp
...\.........\posttrc.log
...\.........\runXst_tcl.rsp
...\.........\TH-UNION+.gfl
...\.........\TH-UNION+_flowplus.gfl
...\.........\tozp_tcl.rsp
...\.........\zhang.gfl
...\.........\zhang_flowplus.gfl
...\__projnav.log
...\xst\work\sub00
...\...\work
...\xst
...\_ngo
...\__projnav
CPU