Description: // Serial Peripheral Interface (SPI)
// The VSPI core implements an SPI interface compatible with the many
// serial EEPROMs, and microcontrollers. The VSPI core is typically used
// as an SPI master, but it can be configured as an SPI slave as well.
//
// The SPI bus is a 3 wire bus that in effect links a serial shift
// register between the "master" and the "slave". Typically both the
// master and slave have an 8 bit shift register so the combined
// register is 16 bits. When an SPI transfer takes place, the master and
// slave shift their shift registers 8 bits and thus exchange their 8
// bit register values.
//
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vspi.v
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