OpenMIPS_VerilogHDL_Study_v1.1\min_sopc\data_ram.v
..............................\........\inst_rom.v
..............................\........\openmips_min_sopc.v
..............................\openmips模块连接关系图.vsd
..............................\rtl\cp0_reg.v
..............................\...\ctrl.v
..............................\...\defines.v
..............................\...\div.v
..............................\...\ex.v
..............................\...\ex_mem.v
..............................\...\hilo_reg.v
..............................\...\id.v
..............................\...\id_ex.v
..............................\...\if_id.v
..............................\...\LLbit_reg.v
..............................\...\mem.v
..............................\...\mem_wb.v
..............................\...\openmips.v
..............................\...\pc_reg.v
..............................\...\regfile.v
..............................\testbench\openmips_min_sopc_tb.v
..............................\min_sopc
..............................\rtl
..............................\testbench
OpenMIPS_VerilogHDL_Study_v1.1