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Title: adder5 Download
 Description: 5 bit full adder, compared with a 4 bit full adder for the novice can be more profound understanding of Verilog language.
 Downloaders recently: [More information of uploader Tomy]
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File list (Check if you may need any files):
 

adder5\adder5.asm.rpt
......\adder5.done
......\adder5.eda.rpt
......\adder5.fit.rpt
......\adder5.fit.smsg
......\adder5.fit.summary
......\adder5.flow.rpt
......\adder5.map.rpt
......\adder5.map.summary
......\adder5.pin
......\adder5.qpf
......\adder5.qsf
......\adder5.sof
......\adder5.sta.rpt
......\adder5.sta.summary
......\adder5.v
......\adder5_nativelink_simulation.rpt
......\adder_tp.v
......\adder_tp.v.bak
......\db\adder5.amm.cdb
......\..\adder5.asm.qmsg
......\..\adder5.asm.rdb
......\..\adder5.asm_labs.ddb
......\..\adder5.cbx.xml
......\..\adder5.cmp.bpm
......\..\adder5.cmp.cbp
......\..\adder5.cmp.cdb
......\..\adder5.cmp.hdb
......\..\adder5.cmp.kpt
......\..\adder5.cmp.logdb
......\..\adder5.cmp.rdb
......\..\adder5.cmp_merge.kpt
......\..\adder5.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
......\..\adder5.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
......\..\adder5.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
......\..\adder5.db_info
......\..\adder5.eda.qmsg
......\..\adder5.fit.qmsg
......\..\adder5.hier_info
......\..\adder5.hif
......\..\adder5.idb.cdb
......\..\adder5.lpc.html
......\..\adder5.lpc.rdb
......\..\adder5.lpc.txt
......\..\adder5.map.bpm
......\..\adder5.map.cbp
......\..\adder5.map.cdb
......\..\adder5.map.hdb
......\..\adder5.map.kpt
......\..\adder5.map.logdb
......\..\adder5.map.qmsg
......\..\adder5.map_bb.cdb
......\..\adder5.map_bb.hdb
......\..\adder5.map_bb.logdb
......\..\adder5.pre_map.cdb
......\..\adder5.pre_map.hdb
......\..\adder5.rtlv.hdb
......\..\adder5.rtlv_sg.cdb
......\..\adder5.rtlv_sg_swap.cdb
......\..\adder5.sgdiff.cdb
......\..\adder5.sgdiff.hdb
......\..\adder5.sld_design_entry.sci
......\..\adder5.sld_design_entry_dsc.sci
......\..\adder5.smart_action.txt
......\..\adder5.sta.qmsg
......\..\adder5.sta.rdb
......\..\adder5.sta_cmp.7_slow_1200mv_85c.tdb
......\..\adder5.syn_hier_info
......\..\adder5.tiscmp.fast_1200mv_0c.ddb
......\..\adder5.tiscmp.slow_1200mv_0c.ddb
......\..\adder5.tiscmp.slow_1200mv_85c.ddb
......\..\adder5.tis_db_list.ddb
......\..\adder5.tmw_info
......\..\logic_util_heursitic.dat
......\..\prev_cmp_adder5.qmsg
......\incremental_db\compiled_partitions\adder5.db_info
......\..............\...................\adder5.root_partition.cmp.cdb
......\..............\...................\adder5.root_partition.cmp.dfp
......\..............\...................\adder5.root_partition.cmp.hdb
......\..............\...................\adder5.root_partition.cmp.kpt
......\..............\...................\adder5.root_partition.cmp.logdb
......\..............\...................\adder5.root_partition.cmp.rcfdb
......\..............\...................\adder5.root_partition.cmp.re.rcfdb
......\..............\...................\adder5.root_partition.map.cdb
......\..............\...................\adder5.root_partition.map.dpi
......\..............\...................\adder5.root_partition.map.hdb
......\..............\...................\adder5.root_partition.map.kpt
......\..............\README
......\simulation\modelsim\adder5.sft
......\..........\........\adder5.vo
......\..........\........\adder5_7_1200mv_0c_slow.vo
......\..........\........\adder5_7_1200mv_0c_v_slow.sdo
......\..........\........\adder5_7_1200mv_85c_slow.vo
......\..........\........\adder5_7_1200mv_85c_v_slow.sdo
......\..........\........\adder5_min_1200mv_0c_fast.vo
......\..........\........\adder5_min_1200mv_0c_v_fast.sdo
......\..........\........\adder5_modelsim.xrf
......\..........\........\adder5_run_msim_rtl_verilog.do
......\..........\........\adder5_run_msim_rtl_verilog.do.bak
......\..........\........\adder5_run_msim_rtl_verilog.do.bak1
    

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