Description: An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder
Architecture of adders based on speed, area and power dissipation
Design of high speed hybrid carry select adder
High speed Dual Mode Logic Carry Look Ahead Adder
Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer
New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A
New structure for adder with improved speed, area and power
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder.pdf |
| Architecture of adders based on speed | area and power dissipation.pdf |
| Design of high speed hybrid carry select adder.pdf |
| High speed Dual Mode Logic Carry Look Ahead Adder.pdf |
| Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer.pdf |
| New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A.pdf |
| New structure for adder with improved speed | area and power.pdf |
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