Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: dds Download
 Description: Can be achieved via a serial port configuration of DDS, mono mode, the output frequency is 50 m.Have been debugging, can use directly
 Downloaders recently: [More information of uploader 程序]
 To Search:
File list (Check if you may need any files):
 

dds
...\ad9910 configuration.txt
    

CodeBus www.codebus.net