uart最终\clkdiv.v
........\clkdiv.v.bak
........\clkdivTest.v
........\clkdivTest.v.bak
........\pclk.v.bak
........\UART.v
........\UART.v.bak
........\UARTtb.v
........\UARTtb.v.bak
........\UART_r.v
........\UART_r.v.bak
........\UART_rTEST
........\UART_rTEST.bak
........\UART_rTEST.v
........\UART_rTEST.v.bak
........\UART_t.v
........\UART_t.v.bak
........\UART_tTEST.v
........\UART_tTEST.v.bak
........\work\@clk@div\verilog.asm
........\....\........\verilog.rw
........\....\........\_primary.dat
........\....\........\_primary.dbs
........\....\........\_primary.vhd
........\....\........@test\verilog.asm
........\....\.............\verilog.rw
........\....\.............\_primary.dat
........\....\.............\_primary.dbs
........\....\.............\_primary.vhd
........\....\._opt\vopt30anrh
........\....\.....\vopt60kch3
........\....\.....\vopt7jvabg
........\....\.....\voptaj5142
........\....\.....\voptdjfqwj
........\....\.....\vopte6qmn0
........\....\.....\vopth61cfi
........\....\.....\voptk6b284
........\....\.....\voptmsi02h
........\....\.....\voptrswnt2
........\....\.....\voptvs6djk
........\....\.....\voptwcebd1
........\....\.....\voptzcr16j
........\....\.....\_deps
........\....\clkdiv\verilog.asm
........\....\......\verilog.rw
........\....\......\_primary.dat
........\....\......\_primary.dbs
........\....\......\_primary.vhd
........\....\......@test\verilog.asm
........\....\...........\verilog.rw
........\....\...........\_primary.dat
........\....\...........\_primary.dbs
........\....\...........\_primary.vhd
........\....\_info
........\....\.temp\vlog65nbhw
........\....\.....\vlogbxvafz
........\....\.....\vlogcz9z07
........\....\.....\vlogk628bm
........\....\.....\vlogm50jds
........\....\.....\vlogq2irdc
........\....\.....\vlogsy12wx
........\....\.....\vlogwbqcfs
........\....\.....\vlogxtdqz6
........\....\_vmake
........\....\@clk@div
........\....\@clk@div@test
........\....\@_opt
........\....\clkdiv
........\....\clkdiv@test
........\....\_temp
........\work
uart最终