Description: The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full adder.
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File list (Check if you may need any files):
四位二进制加法器\exp5\exp5\db\exp5.asm.qmsg
................\....\....\..\exp5.cbx.xml
................\....\....\..\exp5.cmp.cdb
................\....\....\..\exp5.cmp.hdb
................\....\....\..\exp5.cmp.logdb
................\....\....\..\exp5.cmp.rdb
................\....\....\..\exp5.cmp.tdb
................\....\....\..\exp5.cmp0.ddb
................\....\....\..\exp5.dbp
................\....\....\..\exp5.db_info
................\....\....\..\exp5.eco.cdb
................\....\....\..\exp5.eds_overflow
................\....\....\..\exp5.fit.qmsg
................\....\....\..\exp5.fnsim.hdb
................\....\....\..\exp5.fnsim.qmsg
................\....\....\..\exp5.hier_info
................\....\....\..\exp5.hif
................\....\....\..\exp5.map.cdb
................\....\....\..\exp5.map.hdb
................\....\....\..\exp5.map.logdb
................\....\....\..\exp5.map.qmsg
................\....\....\..\exp5.pre_map.cdb
................\....\....\..\exp5.pre_map.hdb
................\....\....\..\exp5.psp
................\....\....\..\exp5.pss
................\....\....\..\exp5.rpp.qmsg
................\....\....\..\exp5.rtlv.hdb
................\....\....\..\exp5.rtlv_sg.cdb
................\....\....\..\exp5.rtlv_sg_swap.cdb
................\....\....\..\exp5.sgate.rvd
................\....\....\..\exp5.sgate_sm.rvd
................\....\....\..\exp5.sgdiff.cdb
................\....\....\..\exp5.sgdiff.hdb
................\....\....\..\exp5.sim.cvwf
................\....\....\..\exp5.sim.qmsg
................\....\....\..\exp5.sim.rdb
................\....\....\..\exp5.sld_design_entry.sci
................\....\....\..\exp5.sld_design_entry_dsc.sci
................\....\....\..\exp5.syn_hier_info
................\....\....\..\exp5.tan.qmsg
................\....\....\..\prev_cmp_exp5.asm.qmsg
................\....\....\..\prev_cmp_exp5.fit.qmsg
................\....\....\..\prev_cmp_exp5.map.qmsg
................\....\....\..\prev_cmp_exp5.sim.qmsg
................\....\....\..\prev_cmp_exp5.tan.qmsg
................\....\....\..\wed.wsf
................\....\....\exp5.asm.rpt
................\....\....\exp5.cdf
................\....\....\exp5.done
................\....\....\exp5.dpf
................\....\....\exp5.fit.rpt
................\....\....\exp5.fit.summary
................\....\....\exp5.flow.rpt
................\....\....\exp5.map.rpt
................\....\....\exp5.map.summary
................\....\....\exp5.pin
................\....\....\exp5.pof
................\....\....\exp5.qpf
................\....\....\exp5.qsf
................\....\....\exp5.qws
................\....\....\exp5.sim.rpt
................\....\....\exp5.sof
................\....\....\exp5.tan.rpt
................\....\....\exp5.tan.summary
................\....\....\exp5.vhd.bak
................\....\....\exp5.vwf
................\....\....\FULL_4ADDER.vhd
................\....\....\FULL_4ADDER.vhd.bak
................\....\....\FULL_4ADDER.vwf
................\....\....\FULL_ADDER.vhd
................\....\....\FULL_ADDER.vhd.bak
................\....\....\FULL_ADDER.vwf
................\....\....\HALF_ADDER.vhd
................\....\....\HALF_ADDER.vhd.bak
................\....\....\prev_cmp_exp5.qmsg
................\....\....\serv_req_info.txt
................\....\Thumbs.db
................\....\~$P 5 电子信息工程121 袁翀志 12610126.docx
................\....\引脚分配图.jpg
................\....\硬件验证结果.jpg
................\....\系统仿真结果.jpg
................\....\系统仿真结果2.jpg
................\GENERATE_4ADDER\GENERATE_4ADDER\ADDER.vhd
................\...............\...............\ADDER.vhd.bak
................\...............\...............\db\GENERATE_4ADDER.asm.qmsg
................\...............\...............\..\GENERATE_4ADDER.cbx.xml
................\...............\...............\..\GENERATE_4ADDER.cmp.cdb
................\...............\...............\..\GENERATE_4ADDER.cmp.hdb
................\...............\...............\..\GENERATE_4ADDER.cmp.logdb
................\
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