- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 381kb
- Update:
- 2013-12-23
- Downloads:
- 0 Times
- Uploaded by:
- 痴心
Description: Design of 16-bit arithmetic logic unit, to add, subtract, add 1, subtract 1, AND, OR, NOT, transfer function.
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alu1
....\alu1.asm.rpt
....\alu1.done
....\alu1.dpf
....\alu1.fit.rpt
....\alu1.fit.smsg
....\alu1.fit.summary
....\alu1.flow.rpt
....\alu1.map.rpt
....\alu1.map.summary
....\alu1.pin
....\alu1.pof
....\alu1.qpf
....\alu1.qsf
....\alu1.sof
....\alu1.tan.rpt
....\alu1.tan.summary
....\alu1.vhd
....\alu1.vhd.bak
....\db
....\..\alu1.asm.qmsg
....\..\alu1.cbx.xml
....\..\alu1.cmp.bpm
....\..\alu1.cmp.cdb
....\..\alu1.cmp.ecobp
....\..\alu1.cmp.hdb
....\..\alu1.cmp.logdb
....\..\alu1.cmp.rdb
....\..\alu1.cmp.tdb
....\..\alu1.cmp0.ddb
....\..\alu1.cmp_bb.cdb
....\..\alu1.cmp_bb.hdb
....\..\alu1.cmp_bb.logdb
....\..\alu1.cmp_bb.rcf
....\..\alu1.db_info
....\..\alu1.dbp
....\..\alu1.eco.cdb
....\..\alu1.fit.qmsg
....\..\alu1.hier_info
....\..\alu1.hif
....\..\alu1.map.bpm
....\..\alu1.map.cdb
....\..\alu1.map.ecobp
....\..\alu1.map.hdb
....\..\alu1.map.logdb
....\..\alu1.map.qmsg
....\..\alu1.map_bb.cdb
....\..\alu1.map_bb.hdb
....\..\alu1.map_bb.logdb
....\..\alu1.pre_map.cdb
....\..\alu1.pre_map.hdb
....\..\alu1.psp
....\..\alu1.pss
....\..\alu1.rtlv.hdb
....\..\alu1.rtlv_sg.cdb
....\..\alu1.rtlv_sg_swap.cdb
....\..\alu1.sgdiff.cdb
....\..\alu1.sgdiff.hdb
....\..\alu1.signalprobe.cdb
....\..\alu1.sld_design_entry.sci
....\..\alu1.sld_design_entry_dsc.sci
....\..\alu1.syn_hier_info
....\..\alu1.tan.qmsg
....\..\alu1.tis_db_list.ddb
....\..\prev_cmp_alu1.asm.qmsg
....\..\prev_cmp_alu1.fit.qmsg
....\..\prev_cmp_alu1.map.qmsg
....\..\prev_cmp_alu1.qmsg
....\..\prev_cmp_alu1.tan.qmsg