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Title: bmd_design Download
 Description: Verify that the DMA transfer process, pin binding interface part can be modified based on XILINX VC6LX550T FPGA development according to its own chip models xapp1052
 Downloaders recently: [More information of uploader aj]
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bmd_design\bmd_design.gise
..........\bmd_design.xise
..........\ipcore_dir\bmd_design\dma_performance_demo\fpga\BMD\BMD_128_RX_ENGINE.v
..........\..........\..........\....................\....\...\BMD_128_TX_ENGINE.v
..........\..........\..........\....................\....\...\BMD_32_RX_ENGINE.v
..........\..........\..........\....................\....\...\BMD_32_TX_ENGINE.v
..........\..........\..........\....................\....\...\BMD_64_RX_ENGINE.v
..........\..........\..........\....................\....\...\BMD_64_TX_ENGINE.v
..........\..........\..........\....................\....\...\common\BMD.v
..........\..........\..........\....................\....\...\......\BMD_CFG_CTRL.v
..........\..........\..........\....................\....\...\......\BMD_EP.v
..........\..........\..........\....................\....\...\......\BMD_EP_MEM.v
..........\..........\..........\....................\....\...\......\BMD_EP_MEM_ACCESS.v
..........\..........\..........\....................\....\...\......\BMD_GEN2.v
..........\..........\..........\....................\....\...\......\BMD_INTR_CTRL.v
..........\..........\..........\....................\....\...\......\BMD_INTR_CTRL_DELAY.v
..........\..........\..........\....................\....\...\......\BMD_PCIE_20.v
..........\..........\..........\....................\....\...\......\BMD_RD_THROTTLE.v
..........\..........\..........\....................\....\...\......\BMD_TO_CTRL.v
..........\..........\..........\....................\....\...\pipe_1_lane_pci_exp_32b_app.v
..........\..........\..........\....................\....\...\s6_pci_exp_32b_app.v
..........\..........\..........\....................\....\...\v5_blk_plus_pci_exp_64b_app.v
..........\..........\..........\....................\....\...\v6_pci_exp_128b_app.v
..........\..........\..........\....................\....\...\v6_pci_exp_64b_app.v
..........\..........\..........\....................\....\implement\esults.bld
..........\..........\..........\....................\....\.........\implement_dma.pl
..........\..........\..........\....................\....\.........\implement_dma_backup.pl
..........\..........\..........\....................\....\.........\netlist.lst
..........\..........\..........\....................\....\.........\results\mapped.map
..........\..........\..........\....................\....\.........\.......\mapped.mrp
..........\..........\..........\....................\....\.........\.......\mapped.ncd
..........\..........\..........\....................\....\BMD\common
..........\..........\..........\....................\....\implement\results
..........\..........\..........\....................\....\BMD
..........\..........\..........\....................\....\implement
..........\..........\..........\....................\fpga
..........\..........\..........\dma_performance_demo
..........\..........\bmd_design
..........\ipcore_dir
bmd_design
    

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