RD1169
......\constraints
......\doc
......\...\RD1169.pdf
......\...\README_Simulation.txt
......\...\README_Synthesis.txt
......\project
......\.......\UART_16450_Transceiver
......\.......\......................\UART_16450_Transceiver_sbt.project
......\.......\......................\UART_16450_Transceiver_syn.prj
......\simulation
......\..........\aldec
......\..........\.....\RD1169.do
......\source
......\......\Verilog
......\......\.......\uart_16450_reg.v
......\......\.......\uart_16450_transceiver.v
......\......\.......\uart_master_controller.v
......\......\.......\uart_rx_fsm.v
......\......\.......\uart_transceiver.v
......\......\.......\uart_tx_fsm.v
......\testbench
......\.........\Verilog
......\.........\.......\globalvariables.v
......\.........\.......\loopback.v
......\.........\.......\readdatabuffer.v
......\.........\.......\readintridreg.v
......\.........\.......\readlinestatusreg.v
......\.........\.......\readmodemstatus.v
......\.........\.......\rxdatapathchk.v
......\.........\.......\sb_ice_lc.v
......\.........\.......\sb_ice_syn.v
......\.........\.......\setbaudrate.v
......\.........\.......\setdivisorlatch.v
......\.........\.......\setintrreg.v
......\.........\.......\setlinecntrlreg.v
......\.........\.......\setmodemcntrlreg.v
......\.........\.......\settxholdingreg.v
......\.........\.......\simulationdone.v
......\.........\.......\systasks.v
......\.........\.......\testcase.v
......\.........\.......\txdatapathchk.v
......\.........\.......\uart_16450_transceiver_tb.v
......\.........\.......\uart_16450_transceiver_wrapper.v
......\.........\.......\UART_16450_Transceiver_wrapper_synth.v