- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 184kb
- Update:
- 2014-01-14
- Downloads:
- 0 Times
- Uploaded by:
- 卢进
Description: An FPGA-based variable step-down counter applet, a clock input, add, subtract control signal, the conversion result.
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File list (Check if you may need any files):
Example7
........\db
........\exp7.asm.rpt
........\exp7.done
........\exp7.dpf
........\exp7.eda.rpt
........\exp7.fit.rpt
........\exp7.fit.smsg
........\exp7.fit.summary
........\exp7.flow.rpt
........\exp7.map.rpt
........\exp7.map.summary
........\exp7.pin
........\exp7.pof
........\exp7.qpf
........\exp7.qsf
........\exp7.qws
........\exp7.sof
........\exp7.sta.rpt
........\exp7.sta.summary
........\exp7.tan.rpt
........\exp7.tan.summary
........\exp7.vhd
........\exp7.vhd.bak
........\incremental_db
........\..............\README
........\..............\compiled_partitions
........\..............\...................\exp7.root_partition.cmp.atm
........\..............\...................\exp7.root_partition.cmp.dfp
........\..............\...................\exp7.root_partition.cmp.hdbx
........\..............\...................\exp7.root_partition.cmp.kpt
........\..............\...................\exp7.root_partition.cmp.logdb
........\..............\...................\exp7.root_partition.cmp.rcf
........\..............\...................\exp7.root_partition.map.atm
........\..............\...................\exp7.root_partition.map.dpi
........\..............\...................\exp7.root_partition.map.hdbx
........\..............\...................\exp7.root_partition.map.kpt
........\simulation
........\..........\modelsim
........\..........\........\exp7.sft
........\..........\........\exp7.vho
........\..........\........\exp7_8_1200mv_0c_vhd_slow.sdo
........\..........\........\exp7_8_1200mv_85c_vhd_slow.sdo
........\..........\........\exp7_min_1200mv_0c_vhd_fast.sdo
........\..........\........\exp7_modelsim.xrf
........\..........\........\exp7_vhd.sdo
........\timing
........\......\primetime
........\......\.........\exp7.collections.sdc
........\......\.........\exp7.constraints.sdc
........\......\.........\exp7.pt.tcl
........\......\.........\exp7.vo
........\......\.........\exp7_8_1200mv_0c_v_slow.sdo
........\......\.........\exp7_8_1200mv_85c_v_slow.sdo
........\......\.........\exp7_min_1200mv_0c_v_fast.sdo
........\......\.........\exp7_pt_v.tcl
........\......\.........\exp7_v.sdo
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