- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2014-02-17
- Downloads:
- 0 Times
- Uploaded by:
- 郭先生
Description: uart receive asynchronous serial module, serial data will be combined to become 8 bytes. The baud rate of self-regulation
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rxpart.vhd