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Software Engineering
Title:
2
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Category:
Project Design
Tags:
[VHDL]
[源码]
File Size:
1kb
Update:
2014-02-23
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Uploaded by:
Srikanth
Description:
Verilog Code By sivanantham and sakthivel Lab assignment-xor gate Do not forget to thank
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nand_gate.v odd_parg.v odd_pard.v odd_par_tst.v nor_gate.v
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