- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 19kb
- Update:
- 2014-03-05
- Downloads:
- 1 Times
- Uploaded by:
- 毛子明
Description: AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
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AES加密_解密_verilog代码.docx
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