Description:
Binary to BCD s verilog procedures to achieve binary number to BCD conversion, the program has an internal FPGA logic resources saving features
To Search:
File list (Check if you may need any files):
t1_bin2bcd
..........\bcd_encoder.bsf
..........\bcd_encoder_modify.bsf
..........\bcd_encoder_single.v
..........\bcd_encoder_single.v.bak
..........\bcd_encoder_single_modify.bsf
..........\bcd_encoder_tb.v
..........\bcd_encoder_tb.v.bak
..........\db
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_t1.qmsg
..........\..\t1.amm.cdb
..........\..\t1.asm.qmsg
..........\..\t1.asm.rdb
..........\..\t1.asm_labs.ddb
..........\..\t1.cbx.xml
..........\..\t1.cmp.bpm
..........\..\t1.cmp.cdb
..........\..\t1.cmp.hdb
..........\..\t1.cmp.kpt
..........\..\t1.cmp.logdb
..........\..\t1.cmp.rdb
..........\..\t1.cmp0.ddb
..........\..\t1.cmp1.ddb
..........\..\t1.cmp2.ddb
..........\..\t1.cmp_merge.kpt
..........\..\t1.db_info
..........\..\t1.eda.qmsg
..........\..\t1.fit.qmsg
..........\..\t1.hier_info
..........\..\t1.hif
..........\..\t1.idb.cdb
..........\..\t1.lpc.html
..........\..\t1.lpc.rdb
..........\..\t1.lpc.txt
..........\..\t1.map.bpm
..........\..\t1.map.cdb
..........\..\t1.map.hdb
..........\..\t1.map.kpt
..........\..\t1.map.logdb
..........\..\t1.map.qmsg
..........\..\t1.map.rdb
..........\..\t1.map_bb.cdb
..........\..\t1.map_bb.hdb
..........\..\t1.map_bb.logdb
..........\..\t1.pre_map.cdb
..........\..\t1.pre_map.hdb
..........\..\t1.root_partition.map.reg_db.cdb
..........\..\t1.routing.rdb
..........\..\t1.rtlv.hdb
..........\..\t1.rtlv_sg.cdb
..........\..\t1.rtlv_sg_swap.cdb
..........\..\t1.sgdiff.cdb
..........\..\t1.sgdiff.hdb
..........\..\t1.sld_design_entry.sci
..........\..\t1.sld_design_entry_dsc.sci
..........\..\t1.smart_action.txt
..........\..\t1.sta.qmsg
..........\..\t1.sta.rdb
..........\..\t1.sta_cmp.8_slow.tdb
..........\..\t1.syn_hier_info
..........\..\t1.tis_db_list.ddb
..........\..\t1.tmw_info
..........\incremental_db
..........\..............\compiled_partitions
..........\..............\...................\t1.db_info
..........\..............\...................\t1.root_partition.cmp.cdb
..........\..............\...................\t1.root_partition.cmp.dfp
..........\..............\...................\t1.root_partition.cmp.hdb
..........\..............\...................\t1.root_partition.cmp.kpt
..........\..............\...................\t1.root_partition.cmp.logdb
..........\..............\...................\t1.root_partition.cmp.rcfdb
..........\..............\...................\t1.root_partition.map.cdb
..........\..............\...................\t1.root_partition.map.dpi
..........\..............\...................\t1.root_partition.map.hbdb.cdb
..........\..............\...................\t1.root_partition.map.hbdb.hb_info
..........\..............\...................\t1.root_partition.map.hbdb.hdb
..........\..............\...................\t1.root_partition.map.hbdb.sig
..........\..............\...................\t1.root_partition.map.hdb
..........\..............\...................\t1.root_partition.map.kpt
..........\..............\README
..........\simulation
..........\..........\modelsim
..........\..........\........\modelsim.ini
..........\..........\........\msim_transcript
..........\..........\........\rtl_work
..........\..........\........\........\bcd_encoder
..........\..........\........\........\...........\verilog.prw
..........\..........\........\........\...........\verilog.psm
..........\..........\........\........\...........\_primary.dat
..........\..........\........\........\...........\_primary.dbs
..........\..........\........\........\...........\_primary.vhd
..........\..........\........\........\bcd_encoder_modify
..........\..........\........\........\..................\verilog.prw
..........\..........\........\........\..................\verilog.psm
..........\..........\........\........\..................\_primary.dat
..........\..........\........\........\..................\_primary.dbs
..........\..........\........\........\..................\_primary.vhd
..........\..........\........\........\bcd_encoder_single_modify
..........\..........\........\........\.........................\verilog.p
Download