- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 31kb
- Update:
- 2014-03-11
- Downloads:
- 0 Times
- Uploaded by:
- 沈湛
Description: Program realizes frequency devision-by-7 of the input clock signal , the program uses two counters, one triggered by the rising edge of the input clock, and the other triggered by the falling edge of the clock.Then I operate "or" arithmetic to the output of two counters.In the last,I obtained the square wave of 50 duty ratio.
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fdiv7.fit.summary
fdiv7.flow.rpt
fdiv7.map.rpt
fdiv7.map.summary
fdiv7.pin
fdiv7.qsf
fdiv7.qws
fdiv7.sim.rpt
fdiv7.tan.rpt
fdiv7.tan.summary
fdiv7.vhd
fdiv7.vhd.bak
fdiv7.asm.rpt
fdiv7.done
fdiv7.dpf
fdiv7.fit.rpt
fdiv7.fit.smsg
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