Description: Reading the image information from the ROM module verilog design control procedures, and then write the VGA connector. Control program every 250ms write different messages to the VGA connector on the screen will appear little green men animated.
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File list (Check if you may need any files):
19_vga\db\altsyncram_1qa1.tdf
......\..\altsyncram_a7a1.tdf
......\..\altsyncram_dni1.tdf
......\..\logic_util_heursitic.dat
......\..\pll_module_altpll.v
......\..\prev_cmp_vga.qmsg
......\..\vga.amm.cdb
......\..\vga.asm.qmsg
......\..\vga.asm.rdb
......\..\vga.asm_labs.ddb
......\..\vga.cbx.xml
......\..\vga.cmp.bpm
......\..\vga.cmp.cdb
......\..\vga.cmp.hdb
......\..\vga.cmp.kpt
......\..\vga.cmp.logdb
......\..\vga.cmp.rdb
......\..\vga.cmp_merge.kpt
......\..\vga.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
......\..\vga.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
......\..\vga.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
......\..\vga.db_info
......\..\vga.fit.qmsg
......\..\vga.hier_info
......\..\vga.hif
......\..\vga.idb.cdb
......\..\vga.lpc.html
......\..\vga.lpc.rdb
......\..\vga.lpc.txt
......\..\vga.map.bpm
......\..\vga.map.cdb
......\..\vga.map.hdb
......\..\vga.map.kpt
......\..\vga.map.logdb
......\..\vga.map.qmsg
......\..\vga.map_bb.cdb
......\..\vga.map_bb.hdb
......\..\vga.map_bb.logdb
......\..\vga.pre_map.cdb
......\..\vga.pre_map.hdb
......\..\vga.rtlv.hdb
......\..\vga.rtlv_sg.cdb
......\..\vga.rtlv_sg_swap.cdb
......\..\vga.sgdiff.cdb
......\..\vga.sgdiff.hdb
......\..\vga.sld_design_entry.sci
......\..\vga.sld_design_entry_dsc.sci
......\..\vga.smart_action.txt
......\..\vga.sta.qmsg
......\..\vga.sta.rdb
......\..\vga.sta_cmp.8_slow_1200mv_85c.tdb
......\..\vga.syn_hier_info
......\..\vga.tiscmp.fastest_slow_1200mv_0c.ddb
......\..\vga.tiscmp.fastest_slow_1200mv_85c.ddb
......\..\vga.tiscmp.fast_1200mv_0c.ddb
......\..\vga.tiscmp.slow_1200mv_0c.ddb
......\..\vga.tiscmp.slow_1200mv_85c.ddb
......\..\vga.tis_db_list.ddb
......\..\vga.tmw_info
......\greenman_rom_module.qip
......\...ybox_tmp\cbx_args.txt
......\incremental_db\compiled_partitions\vga.db_info
......\..............\...................\vga.root_partition.cmp.cdb
......\..............\...................\vga.root_partition.cmp.dfp
......\..............\...................\vga.root_partition.cmp.hdb
......\..............\...................\vga.root_partition.cmp.kpt
......\..............\...................\vga.root_partition.cmp.logdb
......\..............\...................\vga.root_partition.cmp.rcfdb
......\..............\...................\vga.root_partition.map.cdb
......\..............\...................\vga.root_partition.map.dpi
......\..............\...................\vga.root_partition.map.hbdb.cdb
......\..............\...................\vga.root_partition.map.hbdb.hb_info
......\..............\...................\vga.root_partition.map.hbdb.hdb
......\..............\...................\vga.root_partition.map.hbdb.sig
......\..............\...................\vga.root_partition.map.hdb
......\..............\...................\vga.root_partition.map.kpt
......\..............\README
......\PLLJ_PLLSPE_INFO.txt
......\source\greenman.mif
......\......\greenman_rom_module.qip
......\......\greenman_rom_module.v
......\......\greenman_rom_module_bb.v
......\......\greenman_rom_module_inst.v
......\......\pll_module.ppf
......\......\pll_module.qip
......\......\pll_module.v
......\......\pll_module_bb.v
......\......\ram_initial_file.mif
......\......\ram_module.v
......\......\ram_module.v.bak
......\......\sync_module.v
......\......\vga_control_module.v
......\......\vga_interface.v
......\......\vga_interface_demo.v
......\......\vga_interface_demo.v.bak
......\tcl\19_osh.tcl
......\vga.asm.rpt
......\vga.done
......\vga.fit.rpt
......\vga.fit.smsg
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