Description: URAT design, the system consists of five modules, MCU module, TX transmit module, RX accept modules, baud rate generator module, reset module.
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File list (Check if you may need any files):
UART\UART\transcript
....\....\UART.v
....\....\UART_sim.cr.mti
....\....\UART_sim.mpf
....\....\UART_test.v
....\....\UART_top.v
....\....\vsim.wlf
....\....\wave.do
....\....\.ork\@b@c@l@k_gen\verilog.asm
....\....\....\............\_primary.dat
....\....\....\............\_primary.vhd
....\....\....\.m@c@u_@p@o@r@t\verilog.asm
....\....\....\...............\_primary.dat
....\....\....\...............\_primary.vhd
....\....\....\.r@s@t_gen\verilog.asm
....\....\....\..........\_primary.dat
....\....\....\..........\_primary.vhd
....\....\....\...x_data\verilog.asm
....\....\....\.........\_primary.dat
....\....\....\.........\_primary.vhd
....\....\....\.t@x_data\verilog.asm
....\....\....\.........\_primary.dat
....\....\....\.........\_primary.vhd
....\....\....\.u@a@r@t\verilog.asm
....\....\....\........\_primary.dat
....\....\....\........\_primary.vhd
....\....\....\........_test\verilog.asm
....\....\....\.............\_primary.dat
....\....\....\.............\_primary.vhd
....\....\....\..........op\verilog.asm
....\....\....\............\_primary.dat
....\....\....\............\_primary.vhd
....\....\....\_info
....\....\....\@b@c@l@k_gen
....\....\....\@m@c@u_@p@o@r@t
....\....\....\@r@s@t_gen
....\....\....\@r@x_data
....\....\....\@t@x_data
....\....\....\@u@a@r@t
....\....\....\@u@a@r@t_test
....\....\....\@u@a@r@t_top
....\....\work
....\UART
UART
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