Description: FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable
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File list (Check if you may need any files):
BPSK
....\Code
....\....\BPSK.v
....\....\BPSK_tb.v
....\....\BPSK_tb.v.bak
....\....\Fs_Gen.v
....\....\m.v
....\....\SIN14Bit.mif
....\....\SinRom.v
....\Modelsim
....\........\BPSK.cr.mti
....\........\BPSK.mpf
....\........\SIN14Bit.mif
....\........\SIN14Bit.ver
....\........\vsim.wlf
....\........\work
....\........\....\@b@p@s@k
....\........\....\........\verilog.asm
....\........\....\........\verilog.rw
....\........\....\........\_primary.dat
....\........\....\........\_primary.dbs
....\........\....\........\_primary.vhd
....\........\....\@sin@rom
....\........\....\........\verilog.asm
....\........\....\........\verilog.rw
....\........\....\........\_primary.dat
....\........\....\........\_primary.dbs
....\........\....\........\_primary.vhd
....\........\....\fs_@gen
....\........\....\.......\verilog.asm
....\........\....\.......\verilog.rw
....\........\....\.......\_primary.dat
....\........\....\.......\_primary.dbs
....\........\....\.......\_primary.vhd
....\........\....\m_tb
....\........\....\....\verilog.asm
....\........\....\....\verilog.rw
....\........\....\....\_primary.dat
....\........\....\....\_primary.dbs
....\........\....\....\_primary.vhd
....\........\....\wsj
....\........\....\...\verilog.asm
....\........\....\...\verilog.rw
....\........\....\...\_primary.dat
....\........\....\...\_primary.dbs
....\........\....\...\_primary.vhd
....\........\....\_info
....\........\....\_temp
....\........\....\_vmake
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