- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 3kb
- Update:
- 2014-04-11
- Downloads:
- 0 Times
- Uploaded by:
- 白
Description: an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.
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multiply_8_VHDL\add4.vhd
...............\add8.vhd
...............\latch_16.vhd
...............\multi8.vhd
...............\mult_1.vhd
...............\mul_ctrl.vhd
...............\reg_8.vhd
multiply_8_VHDL
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