- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 126kb
- Update:
- 2014-04-17
- Downloads:
- 0 Times
- Uploaded by:
- 泠血
Description: Using VHDL 10 binary counter, teaching examples content in Quartus II 8.1 compiled successfully.
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File list (Check if you may need any files):
CNT10\CNT10.asm.rpt
.....\CNT10.done
.....\CNT10.fit.rpt
.....\CNT10.fit.summary
.....\CNT10.flow.rpt
.....\CNT10.map.rpt
.....\CNT10.map.summary
.....\CNT10.pin
.....\CNT10.pof
.....\CNT10.qpf
.....\CNT10.qsf
.....\CNT10.qws
.....\CNT10.sim.rpt
.....\CNT10.sof
.....\CNT10.tan.rpt
.....\CNT10.tan.summary
.....\CNT10.vhd
.....\CNT10.vwf
.....\CNT10_assignment_defaults.qdf
.....\db\CNT10.asm.qmsg
.....\..\CNT10.cbx.xml
.....\..\CNT10.cmp.cdb
.....\..\CNT10.cmp.hdb
.....\..\CNT10.cmp.logdb
.....\..\CNT10.cmp.rdb
.....\..\CNT10.cmp.tdb
.....\..\CNT10.cmp0.ddb
.....\..\CNT10.db_info
.....\..\CNT10.eco.cdb
.....\..\CNT10.eds_overflow
.....\..\CNT10.fit.qmsg
.....\..\CNT10.hier_info
.....\..\CNT10.hif
.....\..\CNT10.ipinfo
.....\..\CNT10.map.cdb
.....\..\CNT10.map.hdb
.....\..\CNT10.map.logdb
.....\..\CNT10.map.qmsg
.....\..\CNT10.pre_map.cdb
.....\..\CNT10.pre_map.hdb
.....\..\CNT10.rtlv.hdb
.....\..\CNT10.rtlv_sg.cdb
.....\..\CNT10.rtlv_sg_swap.cdb
.....\..\CNT10.sgdiff.cdb
.....\..\CNT10.sgdiff.hdb
.....\..\CNT10.sim.cvwf
.....\..\CNT10.sim.hdb
.....\..\CNT10.sim.qmsg
.....\..\CNT10.sim.rdb
.....\..\CNT10.sld_design_entry.sci
.....\..\CNT10.sld_design_entry_dsc.sci
.....\..\CNT10.syn_hier_info
.....\..\CNT10.tan.qmsg
.....\..\CNT10.tis_db_list.ddb
.....\..\CNT10.tmw_info
.....\..\prev_cmp_CNT10.asm.qmsg
.....\..\prev_cmp_CNT10.fit.qmsg
.....\..\prev_cmp_CNT10.map.qmsg
.....\..\prev_cmp_CNT10.qmsg
.....\..\prev_cmp_CNT10.sim.qmsg
.....\..\prev_cmp_CNT10.tan.qmsg
.....\..\wed.wsf
.....\incremental_db\compiled_partitions\CNT10.db_info
.....\..............\...................\CNT10.root_partition.map.kpt
.....\..............\README
.....\..............\compiled_partitions
.....\db
.....\incremental_db
CNT10