uart_lcd\designer\impl1\designer.log
........\........\.....\designer_synth_check.log
........\........\.....\gen.ide_des
........\........\.....\lcd.ide_des
........\........\.....\rec.ide_des
........\........\.....\send.ide_des
........\........\.....\top.ide_des
........\........\.....\uart_test.adb
........\........\.....\..........dtf\verify.log
........\........\.....\uart_test.ide_des
........\........\.....\uart_test.pdb
........\........\.....\uart_test.pdb.depends
........\........\.....\uart_test.tcl
........\........\.....\uart_test_1.ide_des
........\........\.....\..........._fp\$$FlashPro_10619.L$$
........\........\.....\..............\uart_test.log
........\........\.....\..............\uart_test.pro
........\........\.....\.............._1\$$FlashPro_10619.L$$
........\........\.....\................\uart_test.log
........\........\.....\................\uart_test.pro
........\........\.....\...............2\$$FlashPro_10619.L$$
........\........\.....\................\uart_test.log
........\........\.....\................\uart_test.pro
........\........\.....\...............3\$$FlashPro_10619.L$$
........\........\.....\................\uart_test.log
........\........\.....\................\uart_test.pro
........\........\.....\...............4\$$FlashPro_10619.L$$
........\........\.....\................\uart_test.log
........\........\.....\................\uart_test.pro
........\........\.....\...............5\$$FlashPro_10619.L$$
........\........\.....\................\uart_test.log
........\........\.....\................\uart_test.pro
........\........\.....\...............6\$$FlashPro_10619.L$$
........\........\.....\................\uart_test.log
........\........\.....\................\uart_test.pro
........\........\.....\..........fp\$$FlashPro_10619.L$$
........\........\.....\............\uart_test.log
........\........\.....\............\uart_test.pro
........\hdl\gen.v
........\...\lcd.v
........\...\pl.v
........\...\rec.v
........\...\send.v
........\...\top.v
........\...\uart_test.v
........\simulation\c3f5493e-7961-4b1e-ae12-61c5799f2ab5.tmp
........\..........\modelsim.ini
........\..........\modelsim.ini.sav
........\.martgen\s6c4.xml
........\........\smartgen.aws
........\.ynthesis\.recordref_modgen
........\.........\backup\uart_test.srr
........\.........\dm\uart_test.xdm
........\.........\identify.log
........\.........\run_options.txt
........\.........\scratchproject.prs
........\.........\stdout.log
........\.........\.ynlog\uart_test_Fusion_Mapper.srr
........\.........\......\uart_test_Fusion_Mapper.srr_Min
........\.........\......\uart_test_Fusion_Mapper.szr
........\.........\...tmp\closed.png
........\.........\......\cmdrec_compiler.log
........\.........\......\cmdrec_fusion_mapper.log
........\.........\......\open.png
........\.........\......\uart_test.msg
........\.........\......\uart_test.plg
........\.........\......\uart_test_flink.htm
........\.........\......\uart_test_srr.htm
........\.........\......\uart_test_toc.htm
........\.........\traplog.tlg
........\.........\uart_test.areasrr
........\.........\uart_test.edn
........\.........\uart_test.fse
........\.........\uart_test.htm
........\.........\uart_test.map
........\.........\uart_test.pdc
........\.........\uart_test.sdf
........\.........\uart_test.so
........\.........\uart_test.srd
........\.........\uart_test.srl
........\.........\uart_test.srm
........\.........\uart_test.srr
........\.........\uart_test.srs
........\.........\uart_test.szr
........\.........\uart_test.tlg
........\.........\uart_test_drc.rpt
........\.........\uart_test_sdc.sdc
........\.........\uart_test_syn.prj
........\uart_lcd.prj
........\viewdraw\vf\project.lst
........\........\viewdraw.ini
........\designer\impl1\simulation
........\........\.....\uart_test.dtf
........\........\.....\uart_test_1_fp
........\........\.....\uart_test_1_fp_1
........\........\.....\uart_test_1_fp_2
........\........\.....\uart_test_1_fp_3
........\........\.....\uart_test_1_fp_4
........\........\.....\uart_test_1_fp_5
....