Description: Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
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run_led
.......\Untitled.cfi
.......\Untitled.mcs
.......\Untitled.prm
.......\Untitled.sig
.......\_ngo
.......\....\netlist.lst
.......\_xmsgs
.......\......\bitgen.xmsgs
.......\......\map.xmsgs
.......\......\ngdbuild.xmsgs
.......\......\par.xmsgs
.......\......\pn_parser.xmsgs
.......\......\trce.xmsgs
.......\......\xst.xmsgs
.......\ipcore_dir
.......\iseconfig
.......\.........\led.xreport
.......\.........\led_top.xreport
.......\.........\run_led.projectmgr
.......\led.bgn
.......\led.bit
.......\led.bld
.......\led.cmd_log
.......\led.drc
.......\led.lso
.......\led.ncd
.......\led.ngc
.......\led.ngd
.......\led.ngr
.......\led.pad
.......\led.par
.......\led.pcf
.......\led.prj
.......\led.ptwx
.......\led.stx
.......\led.syr
.......\led.twr
.......\led.twx
.......\led.ucf
.......\led.unroutes
.......\led.ut
.......\led.xpi
.......\led.xst
.......\led_bitgen.xwbt
.......\led_envsettings.html
.......\led_guide.ncd
.......\led_map.map
.......\led_map.mrp
.......\led_map.ncd
.......\led_map.ngm
.......\led_map.xrpt
.......\led_ngdbuild.xrpt
.......\led_pad.csv
.......\led_pad.txt
.......\led_par.xrpt
.......\led_summary.html
.......\led_summary.xml
.......\led_top.v
.......\led_top_summary.html
.......\led_usage.xml
.......\led_xst.xrpt
.......\pa.fromHdl.tcl
.......\planAhead_run_1
.......\...............\planAhead.jou
.......\...............\planAhead.log
.......\...............\planAhead_run.log
.......\...............\run_led.data
.......\...............\............\constrs_1
.......\...............\............\.........\designprops.xml
.......\...............\............\.........\fileset.xml
.......\...............\............\.........\usercols.xml
.......\...............\............\sources_1
.......\...............\............\.........\chipscope.xml
.......\...............\............\.........\fileset.xml
.......\...............\............\.........\ports.xml
.......\...............\............\wt
.......\...............\............\..\webtalk_pa.xml
.......\...............\run_led.ppr
.......\planAhead_run_2
.......\...............\planAhead.jou
.......\...............\planAhead.log
.......\...............\planAhead_run.log
.......\...............\run_led.data
.......\...............\............\constrs_1
.......\...............\............\.........\designprops.xml
.......\...............\............\.........\fileset.xml
.......\...............\............\.........\usercols.xml
.......\...............\............\sources_1
.......\...............\............\.........\chipscope.xml
.......\...............\............\.........\fileset.xml
.......\...............\............\.........\ports.xml
.......\...............\............\wt
.......\...............\............\..\webtalk_pa.xml
.......\...............\run_led.ppr
.......\run_led.gise
.......\run_led.xise
.......\usage_statistics_webtalk.html
.......\webtalk.log
.......\webtalk_pn.xml
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