Description: Development language Verilog, realize spi bus control, internal top-level file, simulation files.
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File list (Check if you may need any files):
SPI_controller_verilog_master\master_model.v
.............................\slave_model.v
.............................\spi_clgen.v
.............................\spi_shift.v
.............................\tb_top.v
.............................\timescale.v
.............................\top.v
.............................\top_defines.v
SPI_controller_verilog_master
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