db
..\logic_util_heursitic.dat
..\prev_cmp_UART.qmsg
..\UART.db_info
..\UART.eco.cdb
..\UART.sld_design_entry.sci
incremental_db
..............\compiled_partitions
..............\...................\UART.root_partition.map.kpt
..............\README
my_uart.v
my_uart.v.bak
output_files
............\UART.asm.rpt
............\UART.done
............\UART.eda.rpt
............\UART.fit.rpt
............\UART.fit.smsg
............\UART.fit.summary
............\UART.flow.rpt
............\UART.jdi
............\UART.map.rpt
............\UART.map.summary
............\UART.pin
............\UART.pof
............\UART.sta.rpt
............\UART.sta.summary
simulation
..........\modelsim
..........\........\modelsim.ini
..........\........\msim_transcript
..........\........\my_uart.vt
..........\........\my_uart.vt.bak
..........\........\rtl_work
..........\........\........\my_uart
..........\........\........\.......\verilog.prw
..........\........\........\.......\verilog.psm
..........\........\........\.......\_primary.dat
..........\........\........\.......\_primary.dbs
..........\........\........\.......\_primary.vhd
..........\........\........\my_uart_vlg_tst
..........\........\........\...............\verilog.prw
..........\........\........\...............\verilog.psm
..........\........\........\...............\_primary.dat
..........\........\........\...............\_primary.dbs
..........\........\........\...............\_primary.vhd
..........\........\........\speed_select
..........\........\........\............\verilog.prw
..........\........\........\............\verilog.psm
..........\........\........\............\_primary.dat
..........\........\........\............\_primary.dbs
..........\........\........\............\_primary.vhd
..........\........\........\uart_rx
..........\........\........\.......\verilog.prw
..........\........\........\.......\verilog.psm
..........\........\........\.......\_primary.dat
..........\........\........\.......\_primary.dbs
..........\........\........\.......\_primary.vhd
..........\........\........\uart_tx
..........\........\........\.......\verilog.prw
..........\........\........\.......\verilog.psm
..........\........\........\.......\_primary.dat
..........\........\........\.......\_primary.dbs
..........\........\........\.......\_primary.vhd
..........\........\........\_info
..........\........\........\_temp
..........\........\........\_vmake
..........\........\UART.sft
..........\........\UART.vo
..........\........\UART_modelsim.xrf
..........\........\UART_run_msim_rtl_verilog.do
..........\........\UART_run_msim_rtl_verilog.do.bak
..........\........\UART_run_msim_rtl_verilog.do.bak1
..........\........\UART_v.sdo
..........\........\vsim.wlf
speed_select.v
speed_select.v.bak
UART.out.sdc
UART.qpf
UART.qsf
UART.qws
UART_description.txt
UART_nativelink_simulation.rpt
uart_rx.v
uart_tx.v
uart_tx.v.bak