Description: This my own design of a light water program in ise10.1 do Verilog programming environment with Spartan3E basys2 development board can achieve eight led lights rst design cycle has a reset key is to use a crossover design is here d trigger realization of 50MHz 50M Divide
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File list (Check if you may need any files):
VGA1\device_usage_statistics.html
....\vga1.bgn
....\vga1.bit
....\VGA1.bld
....\VGA1.cmd_log
....\vga1.drc
....\VGA1.ise
....\VGA1.lso
....\VGA1.ncd
....\VGA1.ngc
....\VGA1.ngd
....\VGA1.ngr
....\VGA1.ntrc_log
....\VGA1.pad
....\VGA1.par
....\VGA1.pcf
....\VGA1.prj
....\VGA1.ptwx
....\VGA1.restore
....\VGA1.stx
....\VGA1.syr
....\VGA1.twr
....\VGA1.twx
....\VGA1.unroutes
....\VGA1.ut
....\VGA1.v
....\VGA1.xpi
....\VGA1.xst
....\VGA1_guide.ncd
....\VGA1_map.map
....\VGA1_map.mrp
....\VGA1_map.ncd
....\VGA1_map.ngm
....\VGA1_map.xrpt
....\VGA1_ngdbuild.xrpt
....\VGA1_pad.csv
....\VGA1_pad.txt
....\VGA1_par.xrpt
....\VGA1_prev_built.ngd
....\VGA1_summary.html
....\VGA1_summary.xml
....\VGA1_usage.xml
....\.....xdb\cst.xbcd
....\........\tmp\ise\version
....\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
....\........\...\...\............\..................\.........\HDProject_StrTbl
....\........\...\...\............\..................\__stored_object_table__
....\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
....\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
....\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
....\........\...\...\............\................\................\dpm_project_main_StrTbl
....\........\...\...\............\................\__stored_objects__
....\........\...\...\............\................\__stored_objects___StrTbl
....\........\...\...\............\................\__stored_object_table__
....\........\...\...\............\................Gui\GuiProjectData
....\........\...\...\............\...................\GuiProjectData_StrTbl
....\........\...\...\............\xreport\Gc_RvReportViewer-Current-Module
....\........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-VGA1
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-VGA1_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
....\........\...\...\..REGISTRY__\Autonym\regkeys
....\........\...\...\............\bitgen\regkeys
....\........\...\...\............\common\regkeys
....\........\...\...\............\.pldfit\regkeys
....\........\...\...\............\Cs\regkeys
....\........\...\...\............\dumpngdio\regkeys
....\........\...\...\............\ExpandedNetlistEngine\regkeys
....\........\...\...\............\fuse\regkeys
....\........\...\...\............\HierarchicalDesign\HDProject\regkeys
....\........\...\...\............\..................\regkeys
....\........\...\...\............\hprep6\regkeys
....\........\...\...\............\idem\regkeys
....\........\...\...\............\map\regkeys
....\........\...\...\............\netgen\regkeys
....\........\...\...\............\.gc2edif\regkeys
....\........\...\...\............\...build\regkeys
....\........\...\...\............\..dbuild\regkeys
....\........\...\...\............\par\regkeys
....\........\...\...\............\ProjectNavigator\regkeys
....\........\...\...\............\................Gui\regkeys
....\........\...\...\............\runner\regkeys
....\........\...\...\............\SrcCtrl\regkeys
....\........\...\...\............\.TE\bitgen\regkeys
....\........\...\...\............\...\map\regkeys
....\........\...\...\............\...\ngdbuild\regkeys
....\........\...\...\............\...\par\regkeys
....\........\...\...\............\...\regkeys
....\........\...\...\............\...\trce\regkeys
....\........\...\...\............\...\xst\regkeys
....\........\...\...\............\taengine\regkeys
....\........\...\...\............\.rce\regkeys
....\........\...\...\............\.sim\regkeys
....\........\...\...\............\vhpcomp\regkeys
....\........\...\...\............\.logcomp\regkeys
....\........\...\...\............\WebTalk\DesignDataCollection\regkeys
....\........\...\...\............\.......\regkeys
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