- Category:
- Project Design
- Tags:
-
- File Size:
- 1kb
- Update:
- 2014-11-08
- Downloads:
- 0 Times
- Uploaded by:
- john
Description: Check all bubbles in the logic diagram. For every bubble that is not compensated by another bubble along the same line, insert an inverter (a one-input NAND gate) or complement the input literal.
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TOFED_Stru
TOFED_Str.vhd
TOFED_Str.vhd.bak
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