Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: shiyan_1 Download
 Description: This a serial prepared using VHDL adder program, easy to use, is essential for beginners
 Downloaders recently: [More information of uploader wzl]
 To Search:
File list (Check if you may need any files):
 

shiyan_1
........\add_1.asm.rpt
........\add_1.bdf
........\add_1.done
........\add_1.fit.rpt
........\add_1.fit.smsg
........\add_1.fit.summary
........\add_1.flow.rpt
........\add_1.jdi
........\add_1.map.rpt
........\add_1.map.summary
........\add_1.pin
........\add_1.pof
........\add_1.qpf
........\add_1.qsf
........\add_1.qws
........\add_1.sim.rpt
........\add_1.sof
........\add_1.sta.rpt
........\add_1.sta.summary
........\add_1.tan.rpt
........\add_1.tan.summary
........\add_1.vwf
........\add_1_assignment_defaults.qdf
........\db
........\..\add_1.amm.cdb
........\..\add_1.asm.qmsg
........\..\add_1.asm.rdb
........\..\add_1.asm_labs.ddb
........\..\add_1.cbx.xml
........\..\add_1.cmp.bpm
........\..\add_1.cmp.cdb
........\..\add_1.cmp.hdb
........\..\add_1.cmp.kpt
........\..\add_1.cmp.logdb
........\..\add_1.cmp.rdb
........\..\add_1.cmp0.ddb
........\..\add_1.cmp1.ddb
........\..\add_1.cmp_merge.kpt
........\..\add_1.db_info
........\..\add_1.fit.qmsg
........\..\add_1.hier_info
........\..\add_1.hif
........\..\add_1.idb.cdb
........\..\add_1.lpc.html
........\..\add_1.lpc.rdb
........\..\add_1.lpc.txt
........\..\add_1.map.bpm
........\..\add_1.map.cdb
........\..\add_1.map.hdb
........\..\add_1.map.kpt
........\..\add_1.map.logdb
........\..\add_1.map.qmsg
........\..\add_1.map.rdb
........\..\add_1.map_bb.cdb
........\..\add_1.map_bb.hdb
........\..\add_1.map_bb.logdb
........\..\add_1.pre_map.cdb
........\..\add_1.pre_map.hdb
........\..\add_1.root_partition.map.reg_db.cdb
........\..\add_1.routing.rdb
........\..\add_1.rtlv.hdb
........\..\add_1.rtlv_sg.cdb
........\..\add_1.rtlv_sg_swap.cdb
........\..\add_1.sgdiff.cdb
........\..\add_1.sgdiff.hdb
........\..\add_1.sim.cvwf
........\..\add_1.sld_design_entry.sci
........\..\add_1.sld_design_entry_dsc.sci
........\..\add_1.smart_action.txt
........\..\add_1.sta.qmsg
........\..\add_1.sta.rdb
........\..\add_1.sta_cmp.6_slow.tdb
........\..\add_1.syn_hier_info
........\..\add_1.tis_db_list.ddb
........\..\add_1_global_asgn_op.abo
........\..\logic_util_heursitic.dat
........\..\prev_cmp_add_1.asm.qmsg
........\..\prev_cmp_add_1.fit.qmsg
........\..\prev_cmp_add_1.map.qmsg
........\..\prev_cmp_add_1.qmsg
........\..\prev_cmp_add_1.sim.qmsg
........\..\prev_cmp_add_1.tan.qmsg
........\..\wed.wsf
........\f_adder.vhd
........\f_adder.vhd.bak
........\h_adder.vhd
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\add_1.db_info
........\..............\...................\add_1.root_partition.cmp.atm
........\..............\...................\add_1.root_partition.cmp.cdb
........\..............\...................\add_1.root_partition.cmp.dfp
........\..............\...................\add_1.root_partition.cmp.hdb
........\..............\...................\add_1.root_partition.cmp.hdbx
........\..............\...................\add_1.root_partition.cmp.kpt
........\..............\...................\add_1.root_partition.cmp.logdb
........\..............\...................\add_1.root_partition.cmp.rcf
........\..............\...................\add_1.root_partition.cmp.rcfdb
........\..............\...................\add_1.root_partition.map.atm
    

CodeBus www.codebus.net