Description: Low-density parity-check (LDPC) codes have recently
emerged due to their excellent performance. However, the
parity check (H) matrices of the previous works are not
adequate for hardware implementation of encoders or
decoders. This paper proposes a hybrid parity check
matrix which is efficient in hardware implementation of
both decoders and encoders. The hybrid H-matrices are
constructed so that both the semi-random technique and
the partly parallel structure can be applied to design
encoders and decoders.
To Search:
File list (Check if you may need any files):
petrinet.ppt
fsmclass.ppt
sequential logic design using xilinx.ppt
fpga.ppt
fpga design flow.ppt
Download