RD1107\docs
......\....\RD1107.pdf
......\....\rd1107_readme.txt
......\project
......\.......\spi_to_pwm.lpf
......\simulation
......\..........\verilog
......\..........\.......\rtl_verilog.do
......\..........\.......\timing_verilog.do
......\source
......\......\verilog
......\......\.......\counter.v
......\......\.......\spi_slave.v
......\......\.......\spi_to_pwm_top.v
......\testbench
......\.........\verilog
......\.........\.......\spi_to_pwm_tb.v
......\.........\.......\spi_wb.v