Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: Random-number-generator-verilog Download
 Description: Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
 Downloaders recently: [More information of uploader sndn_shr]
 To Search:
File list (Check if you may need any files): 
 

110445D_DSD_Individual
......................\110445D_individual report.pdf
......................\13bit_lfsr.circ
......................\13bit_lfsr.jpg
......................\4bit_lfsr.JPG
......................\Code
......................\....\lfsr.v
......................\....\sseg.v
......................\netlist.JPG
......................\RTL_3.png
......................\schematic.pdf
......................\Simulation.JPG
......................\Simulation.wcfg
......................\summary.JPG
......................\tech1.png
......................\testbench
......................\.........\lfsr_rng_test.v
......................\ucf
......................\...\lfsr_rng.ucf

CodeBus www.codebus.net