Description: Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation, source code and so on. For learning reference, hope you upload your own code, improve together, little japanese.
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File list (Check if you may need any files):
T01_UART_CORE
.............\01_Xilinx_Pro
.............\.............\UART_CORE
.............\.............\.........\fuse.log
.............\.............\.........\fuse.xmsgs
.............\.............\.........\fuseRelaunch.cmd
.............\.............\.........\ipcore_dir
.............\.............\.........\iseconfig
.............\.............\.........\.........\UART_CORE.projectmgr
.............\.............\.........\.........\UART_CORE.xreport
.............\.............\.........\isim
.............\.............\.........\isim.cmd
.............\.............\.........\isim.log
.............\.............\.........\....\isim_usage_statistics.html
.............\.............\.........\....\pn_info
.............\.............\.........\....\temp
.............\.............\.........\....\....\@test_@u@a@r@t_@c@o@r@e.sdb
.............\.............\.........\....\....\@u@a@r@t_@c@o@r@e.sdb
.............\.............\.........\....\....\glbl.sdb
.............\.............\.........\....\Test_UART_CORE_isim_beh.exe.sim
.............\.............\.........\....\...............................\isimcrash.log
.............\.............\.........\....\...............................\ISimEngine-DesignHierarchy.dbg
.............\.............\.........\....\...............................\isimkernel.log
.............\.............\.........\....\...............................\netId.dat
.............\.............\.........\....\...............................\Test_UART_CORE_isim_beh.exe
.............\.............\.........\....\...............................\tmp_save
.............\.............\.........\....\...............................\........\_1
.............\.............\.........\....\...............................\work
.............\.............\.........\....\...............................\....\m_00000000000725662178_2338868275.c
.............\.............\.........\....\...............................\....\m_00000000000725662178_2338868275.didat
.............\.............\.........\....\...............................\....\m_00000000000725662178_2338868275.nt.obj
.............\.............\.........\....\...............................\....\m_00000000001158853363_1099395310.c
.............\.............\.........\....\...............................\....\m_00000000001158853363_1099395310.didat
.............\.............\.........\....\...............................\....\m_00000000001158853363_1099395310.nt.obj
.............\.............\.........\....\...............................\....\m_00000000004093713498_2073120511.c
.............\.............\.........\....\...............................\....\m_00000000004093713498_2073120511.didat
.............\.............\.........\....\...............................\....\m_00000000004093713498_2073120511.nt.obj
.............\.............\.........\....\...............................\....\Test_UART_CORE_isim_beh.exe_main.c
.............\.............\.........\....\...............................\....\Test_UART_CORE_isim_beh.exe_main.nt.obj
.............\.............\.........\....\work
.............\.............\.........\....\....\@test_@u@a@r@t_@c@o@r@e.sdb
.............\.............\.........\....\....\@u@a@r@t_@c@o@r@e.sdb
.............\.............\.........\....\....\glbl.sdb
.............\.............\.........\Test_UART_CORE_beh.prj
.............\.............\.........\Test_UART_CORE_isim_beh.exe
.............\.............\.........\Test_UART_CORE_isim_beh.wdb
.............\.............\.........\Test_UART_CORE_stx_beh.prj
.............\.............\.........\UART_CORE.bld
.............\.............\.........\UART_CORE.cmd_log
.............\.............\.........\UART_CORE.gise
.............\.............\.........\UART_CORE.lso
.............\.............\.........\UART_CORE.ngc
.............\.............\.........\UART_CORE.ngd
.............\.............\.........\UART_CORE.ngr
.............\.............\.........\UART_CORE.prj
.............\.............\.........\UART_CORE.stx
.............\.............\.....
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