pud_ben Verilog HDL source code of generating a RO

Title: pud_ben

Description: Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)

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pudn
....\ROM.mif
....\ROM.qip
....\ROM.ver
....\ROM_1.v
....\ROM_bb.v
....\test_benchrom.v

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