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Title: fenpin Download
 Description: Through the FPGA design of frequency divider module, simulation can be passed, for beginners to learn.
 Downloaders recently: [More information of uploader wanchun]
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fenpin
......\db
......\..\fenpin.asm.qmsg
......\..\fenpin.asm_labs.ddb
......\..\fenpin.cbx.xml
......\..\fenpin.cmp.bpm
......\..\fenpin.cmp.cdb
......\..\fenpin.cmp.ecobp
......\..\fenpin.cmp.hdb
......\..\fenpin.cmp.kpt
......\..\fenpin.cmp.logdb
......\..\fenpin.cmp.rdb
......\..\fenpin.cmp.tdb
......\..\fenpin.cmp0.ddb
......\..\fenpin.cmp2.ddb
......\..\fenpin.cmp_merge.kpt
......\..\fenpin.db_info
......\..\fenpin.eco.cdb
......\..\fenpin.eda.qmsg
......\..\fenpin.eds_overflow
......\..\fenpin.fit.qmsg
......\..\fenpin.hier_info
......\..\fenpin.hif
......\..\fenpin.lpc.html
......\..\fenpin.lpc.rdb
......\..\fenpin.lpc.txt
......\..\fenpin.map.bpm
......\..\fenpin.map.cdb
......\..\fenpin.map.ecobp
......\..\fenpin.map.hdb
......\..\fenpin.map.kpt
......\..\fenpin.map.logdb
......\..\fenpin.map.qmsg
......\..\fenpin.map_bb.cdb
......\..\fenpin.map_bb.hdb
......\..\fenpin.map_bb.logdb
......\..\fenpin.pre_map.cdb
......\..\fenpin.pre_map.hdb
......\..\fenpin.rtlv.hdb
......\..\fenpin.rtlv_sg.cdb
......\..\fenpin.rtlv_sg_swap.cdb
......\..\fenpin.sgdiff.cdb
......\..\fenpin.sgdiff.hdb
......\..\fenpin.sim.cvwf
......\..\fenpin.sim.hdb
......\..\fenpin.sim.qmsg
......\..\fenpin.sim.rdb
......\..\fenpin.sld_design_entry.sci
......\..\fenpin.sld_design_entry_dsc.sci
......\..\fenpin.syn_hier_info
......\..\fenpin.tan.qmsg
......\..\fenpin.tis_db_list.ddb
......\..\fenpin.tmw_info
......\..\fenpin_global_asgn_op.abo
......\..\prev_cmp_fenpin.asm.qmsg
......\..\prev_cmp_fenpin.eda.qmsg
......\..\prev_cmp_fenpin.fit.qmsg
......\..\prev_cmp_fenpin.map.qmsg
......\..\prev_cmp_fenpin.qmsg
......\..\prev_cmp_fenpin.sim.qmsg
......\..\prev_cmp_fenpin.tan.qmsg
......\..\wed.wsf
......\fenpin.asm.rpt
......\fenpin.done
......\fenpin.dpf
......\fenpin.eda.rpt
......\fenpin.fit.rpt
......\fenpin.fit.smsg
......\fenpin.fit.summary
......\fenpin.flow.rpt
......\fenpin.map.rpt
......\fenpin.map.summary
......\fenpin.pin
......\fenpin.pof
......\fenpin.qpf
......\fenpin.qsf
......\fenpin.qws
......\fenpin.sft
......\fenpin.sim.rpt
......\fenpin.sof
......\fenpin.tan.rpt
......\fenpin.tan.summary
......\fenpin.v
......\fenpin.v.bak
......\fenpin.vo
......\fenpin.vt
......\fenpin.vwf
......\fenpin_modelsim.xrf
......\fenpin_nativelink_simulation.rpt
......\fenpin_run_msim_rtl_verilog.do
......\fenpin_run_msim_rtl_verilog.do.bak
......\fenpin_run_msim_rtl_verilog.do.bak1
......\fenpin_run_msim_rtl_verilog.do.bak10
......\fenpin_run_msim_rtl_verilog.do.bak11
......\fenpin_run_msim_rtl_verilog.do.bak2
......\fenpin_run_msim_rtl_verilog.do.bak3
......\fenpin_run_msim_rtl_verilog.do.bak4
......\fenpin_run_msim_rtl_verilog.do.bak5
......\fenpin_run_msim_rtl_verilog.do.bak6
......\fenpin_run_msim_rtl_verilog.do.bak7
    

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