Description: write machine code program for 1 to 100 of all natural number can be divisible by 4 and, verify the correctness of the CPU core.
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File list (Check if you may need any files):
test1
.....\db
.....\..\add_sub_7pc.tdf
.....\..\add_sub_8pc.tdf
.....\..\altsyncram_34t.tdf
.....\..\altsyncram_6ms.tdf
.....\..\altsyncram_79i1.tdf
.....\..\altsyncram_b4t.tdf
.....\..\altsyncram_ffs.tdf
.....\..\alt_u_div_eaf.tdf
.....\..\logic_util_heursitic.dat
.....\..\lpm_divide_lkm.tdf
.....\..\lpm_divide_ocm.tdf
.....\..\mult_7dt.tdf
.....\..\prev_cmp_vv_CPU.qmsg
.....\..\sign_div_unsign_dnh.tdf
.....\..\vv_CPU.asm.qmsg
.....\..\vv_CPU.asm.rdb
.....\..\vv_CPU.asm_labs.ddb
.....\..\vv_CPU.cbx.xml
.....\..\vv_CPU.cmp.bpm
.....\..\vv_CPU.cmp.cdb
.....\..\vv_CPU.cmp.hdb
.....\..\vv_CPU.cmp.idb
.....\..\vv_CPU.cmp.kpt
.....\..\vv_CPU.cmp.logdb
.....\..\vv_CPU.cmp.rdb
.....\..\vv_CPU.cmp_merge.kpt
.....\..\vv_CPU.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.....\..\vv_CPU.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
.....\..\vv_CPU.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
.....\..\vv_CPU.db_info
.....\..\vv_CPU.eda.qmsg
.....\..\vv_CPU.fit.qmsg
.....\..\vv_CPU.hier_info
.....\..\vv_CPU.hif
.....\..\vv_CPU.ipinfo
.....\..\vv_CPU.lpc.html
.....\..\vv_CPU.lpc.rdb
.....\..\vv_CPU.lpc.txt
.....\..\vv_CPU.map.ammdb
.....\..\vv_CPU.map.bpm
.....\..\vv_CPU.map.cdb
.....\..\vv_CPU.map.hdb
.....\..\vv_CPU.map.kpt
.....\..\vv_CPU.map.logdb
.....\..\vv_CPU.map.qmsg
.....\..\vv_CPU.map.rdb
.....\..\vv_CPU.map_bb.cdb
.....\..\vv_CPU.map_bb.hdb
.....\..\vv_CPU.map_bb.logdb
.....\..\vv_CPU.pre_map.hdb
.....\..\vv_CPU.pti_db_list.ddb
.....\..\vv_CPU.root_partition.map.reg_db.cdb
.....\..\vv_CPU.routing.rdb
.....\..\vv_CPU.rtlv.hdb
.....\..\vv_CPU.rtlv_sg.cdb
.....\..\vv_CPU.rtlv_sg_swap.cdb
.....\..\vv_CPU.sgdiff.cdb
.....\..\vv_CPU.sgdiff.hdb
.....\..\vv_CPU.sld_design_entry.sci
.....\..\vv_CPU.sld_design_entry_dsc.sci
.....\..\vv_CPU.smart_action.txt
.....\..\vv_CPU.smp_dump.txt
.....\..\vv_CPU.sta.qmsg
.....\..\vv_CPU.sta.rdb
.....\..\vv_CPU.sta_cmp.7_slow_1200mv_85c.tdb
.....\..\vv_CPU.syn_hier_info
.....\..\vv_CPU.tiscmp.fast_1200mv_0c.ddb
.....\..\vv_CPU.tiscmp.slow_1200mv_0c.ddb
.....\..\vv_CPU.tiscmp.slow_1200mv_85c.ddb
.....\..\vv_CPU.tis_db_list.ddb
.....\..\vv_CPU.tmw_info
.....\..\vv_CPU.vpr.ammdb
.....\greybox_tmp
.....\...........\cbx_args.txt
.....\incremental_db
.....\..............\compiled_partitions
.....\..............\...................\vv_CPU.db_info
.....\..............\...................\vv_CPU.root_partition.cmp.ammdb
.....\..............\...................\vv_CPU.root_partition.cmp.cdb
.....\..............\...................\vv_CPU.root_partition.cmp.dfp
.....\..............\...................\vv_CPU.root_partition.cmp.hdb
.....\..............\...................\vv_CPU.root_partition.cmp.kpt
.....\..............\...................\vv_CPU.root_partition.cmp.logdb
.....\..............\...................\vv_CPU.root_partition.cmp.rcfdb
.....\..............\...................\vv_CPU.root_partition.map.cdb
.....\..............\...................\vv_CPU.root_partition.map.dpi
.....\..............\...................\vv_CPU.root_partition.map.hbdb.cdb
.....\..............\...................\vv_CPU.root_partition.map.hbdb.hb_info
.....\..............\...................\vv_CPU.root_partition.map.hbdb.hdb
.....\..............\...................\vv_CPU.root_partition.map.hbdb.sig
.....\..............\...................\vv_CPU.root_partition.map.hdb
.....\..............\...................\vv_CPU.root_partition.map.kpt
.....\..............\README
.....\lab_6mif_1
.....\..........\vv_CPU.mif
.....\lab_6mif_2
.....\..........\GG.bsf
.....\..........\ram.bsf