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Title: Caculator Download
 Description: Verilog language based on simple calculator, to achieve the operation of addition and subtraction, there are modules and constraint files.
 Downloaders recently: [More information of uploader 杨逍]
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计算器
......\ADD_CORE.v
......\CLK_DIV.v
......\CORE_CALCULATE.v
......\DEBOUNCE.v
......\KEY_SCAN.v
......\KEY_SCAN1.v
......\LED_ALU.v
......\LED_SCAN.v
......\LED_TRANS.v
......\SUB_CORE.v
......\TRAN_HEX_LED.v
......\main.ucf
......\main.v
......\tb.v
......\test_core.v
......\v4_dcm.v
    

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