Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: proj1 Download
 Description: EDK project folder for developing simpel appliations
 Downloaders recently: [More information of uploader srin]
 To Search:
File list (Check if you may need any files):
 

proj1\clock_generator_0.log
.....\data\system.ucf
.....\etc\bitgen.ut
.....\...\download.cmd
.....\...\fast_runtime.opt
.....\...\system.filters
.....\...\system.gui
.....\implementation\system_summary.html
.....\system.bsb
.....\system.log
.....\system.make
.....\system.mhs
.....\system.xmp
.....\system_incl.make
.....\__xps\bitinit.opt
.....\.....\edw2xtl_sav_globals.xsl
.....\.....\edw2xtl_sav_view.xsl
.....\.....\edw2xtl_sav_view_addr.xsl
.....\.....\edw2xtl_sav_view_busif.xsl
.....\.....\edw2xtl_sav_view_groups.xsl
.....\.....\edw2xtl_sav_view_port.xsl
.....\.....\gensav_cmd.xml
.....\.....\ise\system.xreport
.....\.....\...\xmsgprops.lst
.....\.....\platgen.opt
.....\.....\simgen.opt
.....\.....\system.xml
.....\.....\xplorer.opt
.....\.....\xpsxflow.opt
.....\.....\ise\_xmsgs
.....\.....\ise
.....\data
.....\etc
.....\implementation
.....\pcores
.....\__xps
proj1
    

CodeBus www.codebus.net