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Title: 10_CMOS_OV7725_RGB640480 Download
 Description: Using FPGA EP4CE developed OV7725 camera video capture system, using Verilog realize
 Downloaders recently: [More information of uploader leeyg]
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10_CMOS_OV7725_RGB640480\core\sdram_pll.bsf
........................\....\sdram_pll.ppf
........................\....\sdram_pll.qip
........................\dev\CMOS_OVxxxx_RGB640480.pti_db_list.ddb
........................\...\CMOS_OVxxxx_RGB640480.qpf
........................\...\CMOS_OVxxxx_RGB640480.qsf
........................\...\CMOS_OVxxxx_RGB640480.qws
........................\...\CMOS_OVxxxx_RGB640480.tcl
........................\...\CMOS_OVxxxx_RGB640480.tis_db_list.ddb
........................\...\PLLJ_PLLSPE_INFO.txt
........................\...\VIP_System.sdc
........................\...\VIP_System.sdc.bak
........................\...\output_files\CMOS_OV7725_RGB640480.jic
........................\...\............\CMOS_OV7725_RGB640480.map
........................\...\............\CMOS_OVxxxx_RGB640480.asm.rpt
........................\...\............\CMOS_OVxxxx_RGB640480.cdf
........................\...\............\CMOS_OVxxxx_RGB640480.done
........................\...\............\CMOS_OVxxxx_RGB640480.fit.rpt
........................\...\............\CMOS_OVxxxx_RGB640480.fit.smsg
........................\...\............\CMOS_OVxxxx_RGB640480.fit.summary
........................\...\............\CMOS_OVxxxx_RGB640480.flow.rpt
........................\...\............\CMOS_OVxxxx_RGB640480.jdi
........................\...\............\CMOS_OVxxxx_RGB640480.map.rpt
........................\...\............\CMOS_OVxxxx_RGB640480.map.smsg
........................\...\............\CMOS_OVxxxx_RGB640480.map.summary
........................\...\............\CMOS_OVxxxx_RGB640480.pin
........................\...\............\CMOS_OVxxxx_RGB640480.pof
........................\...\............\CMOS_OVxxxx_RGB640480.pti_db_list.ddb
........................\...\............\CMOS_OVxxxx_RGB640480.sof
........................\...\............\CMOS_OVxxxx_RGB640480.sta.rpt
........................\...\............\CMOS_OVxxxx_RGB640480.sta.summary
........................\...\............\CMOS_OVxxxx_RGB640480.tis_db_list.ddb
........................\...\............\greybox_tmp\cbx_args.txt
........................\...\............\output_file.map
........................\...\............\sys_pll.qip
........................\...\stp1.stp
........................\...\stp1_auto_stripped.stp
........................\...\stp2.stp
........................\...\stp2_auto_stripped.stp
........................\...\sys_pll.qip
........................\sim\CMOS_Capture_RGB565_TB\CMOS_Capture_RGB565.v
........................\...\......................\CMOS_Capture_RGB565_TB.cr.mti
........................\...\......................\CMOS_Capture_RGB565_TB.mpf
........................\...\......................\CMOS_Capture_RGB565_TB.v
........................\...\......................\Video_Image_Simulate_CMOS.v
........................\...\......................\transcript
........................\...\......................\vsim.wlf
........................\...\......................\wave.do
........................\...\......................\.ork\@c@m@o@s_@capture_@r@g@b565\_primary.dat
........................\...\......................\....\...........................\_primary.dbs
........................\...\......................\....\...........................\_primary.vhd
........................\...\......................\....\...........................\verilog.prw
........................\...\......................\....\...........................\verilog.psm
........................\...\......................\....\..........................._@t@b\_primary.dat
........................\...\......................\....\................................\_primary.dbs
........................\...\......................\....\................................\_primary.vhd
........................\...\......................\....\................................\verilog.prw
........................\...\......................\....\................................\verilog.psm
........................\...\..................

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